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Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 39: MMCM Specification (Cont’d)
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
T MMCMDCK_DI /
T MMCMCKD_DI
T MMCMDCK_DEN /
T MMCMCKD_DEN
T MMCMDCK_DWE /
T MMCMCKD_DWE
DI Setup/Hold
DEN Setup/Hold
DWE Setup/Hold
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00
1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 2.40/0.00
1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 1.43/0.00
ns, Min
ns, Min
ns, Min
T MMCMCKO_DRDY
F DCK
CLK to out of DRDY
DCLK frequency
0.65
200.00
0.72
200.00
0.99
200.00
0.99
200.00
0.70
100.00
ns, Max
MHz, Max
Notes:
1.
2.
3.
4.
5.
6.
The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
The static offset is measured between any MMCM outputs with identical phase.
Values for this parameter are available in the Clocking Wizard.
See w ww.xilinx.com/products/intellectual-property/clocking_wizard.htm .
Includes global clock buffer.
Calculated as F VCO /128 assuming output duty cycle is 50%.
When CLKOUT4_CASCADE = TRUE, MMCM_F OUTMIN is 0.036 MHz.
PLL Switching Characteristics
Table 40: PLL Specification
Speed Grade
Symbol
Description
1.0V
0.9V
Units
-3
-2/-2L
-1
-1M
-2L
PLL_F INMAX
PLL_F INMIN
Maximum Input Clock Frequency
Minimum Input Clock Frequency
1066.00
19.00
933.00
19.00
800.00
19.00
800.00
19.00
800.00
19.00
MHz
MHz
PLL_F INJITTER
Maximum Input Clock Period Jitter
< 20% of clock input period or 1 ns Max
PLL_F INDUTY
PLL_F VCOMIN
PLL_F VCOMAX
PLL_F BANDWIDTH
PLL_T STATPHAOFFSET
Allowable Input Duty Cycle: 19–49 MHz
Allowable Input Duty Cycle: 50–199 MHz
Allowable Input Duty Cycle: 200–399 MHz
Allowable Input Duty Cycle: 400–499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum PLL VCO Frequency
Maximum PLL VCO Frequency
Low PLL Bandwidth at Typical (1)
High PLL Bandwidth at Typical (1)
Static Phase Offset of the PLL Outputs (2)
25.00
30.00
35.00
40.00
45.00
800.00
2133.00
1.00
4.00
0.12
25.00
30.00
35.00
40.00
45.00
800.00
1866.00
1.00
4.00
0.12
25.00
30.00
35.00
40.00
45.00
800.00
1600.00
1.00
4.00
0.12
25.00
30.00
35.00
40.00
45.00
800.00
1600.00
1.00
4.00
0.12
25.00
30.00
35.00
40.00
45.00
800.00
1600.00
1.00
4.00
0.12
%
%
%
%
%
MHz
MHz
MHz
MHz
ns
PLL_T OUTJITTER
PLL Output Jitter
Note 3
PLL_T OUTDUTY
PLL_T LOCKMAX
PLL_F OUTMAX
PLL_F OUTMIN
PLL Output Clock Duty Cycle Precision (4)
PLL Maximum Lock Time
PLL Maximum Output Frequency
PLL Minimum Output Frequency (5)
0.20
100
1066.00
6.25
0.20
100
933.00
6.25
0.20
100
800.00
6.25
0.20
100
800.00
6.25
0.25
100
800.00
6.25
ns
μs
MHz
MHz
PLL_T EXTFDVAR
External Clock Feedback Variation
< 20% of clock input period or 1 ns Max
PLL_RST MINPULSE
Minimum Reset Pulse Width
5.00
5.00
5.00
5.00
5.00
ns
DS182 (v2.8) March 4, 2014
Product Specification
www.xilinx.com
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